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Home > chinese-english > "q channel" in English

English translation for "q channel"

q信道,q-通道
q信号信道


Related Translations:
gao q:  高歧
q aerial:  带四分之一波长匹配线的偶极子无线
q signal:  q信号
q带:  q bnadqbaq-bandquinacrine band
q data:  q资料
coenzyme q:  辅酶q,泛醌辅酶Q辅霉q
q调制:  q-modulation
q coenzyme:  辅酶q
q分类法:  q sort methodq sort technique
q lib:  随意量
Example Sentences:
1.Among the various ways to achieve the demodulation and decimation of i and q channels , the polyphase filter is selected in the paper
Ddc的实现分为两个部分, iq分解和抽取。本文采用的是多项滤波的方式。
2.A new dsp algorithm for doppler frequency measurement is constructed in the second method , where the circuit configuration is simplified , the balanced i / q channels can be available and the time for digital signal processing is reduced
在第二种方案中,提出了一种测量多普勒频移的数字信号处理算法,简化了硬件,获得了平衡的i q信道输出,缩短了dsp处理时间。
3.This paper particularly compares the complexities of the three manners ? the base band complex signal manner 、 the intermediate frequency complex signal manner and the intermediate frequency real signal manner , in the rf circuit and the base band digital signal processing , respectively ; chooses the intermediate frequency complex signal output manner , which not only reduces the complexity of the digital signal processing , but also be compatible with the intermediate frequency real signal output manner in some applications which have strictly request on the consistency of the amplitude and the phase in i / q channels
然而在以往的文献中很少对此进行过全面的分析。论文详细比较了三种不同的信号输出方式? ?基带复信号、中频复信号和中频实信号在rf电路和后端数字信号处理复杂度上的区别;并为接收机选择了中频复信号输出方式,在降低数字信号处理复杂度的同时,还能在某些对i / q双通道幅相一致性要求严格的应用场合兼容中频实信号输出方式。
4.The radar digitalized receiver is based on digital down conversion ( ddc ) technology , which is implemented on fpga . the radar controller is based on the following technologies : fpga , tigersharc dsp and can bus . the implementation of ddc includes two parts , the demodulation and decimation of i and q channels
雷达数字化接收机部分是基于数字下变频( ddc )技术在fpga上实现的算法研究及工程实现;雷达控制器部分是基于tigersharc 、 fpga 、 can总线的多项控制技术的方法研究及实现。
5.The third kind of channels is the asset prices channels , in particular the equity ( stock and bond ) price channels , which include the investment - related tobin ' s q channel and the consumption - related wealth channel . the fourth kind of channels is the exchange rate channel . each channel is related to an implicit financial structure and the financial structure impacts on the scope and relative strength of the concerned kind of monetary transmission channels
第3章根据资金流量帐户,从金融工具的发展速度和顺序、金融总体相关比率和相对比率、金融机构和金融市场的结构和渗透程度、非金融部门(居民、企业和政府)的金融资产负债结构共四大方面,系统地考察了中国金融结构的变迁轨迹,以及以美国为参照系的演变前景。
6.The vxibus c - size and i , q channels are employed in this module design , and the sampling rate in each channel reaches 500mhz . the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ) . the timing and logic function are fulfilled by fpga . after the disscusion of signal adjusted , the detailed scheme of this module design have been showed . in this design , there is much logic function design , and it is very strict with the hardware language program . so the basic flow of hardware program design and several very important methods of high speed logic function design , which is described by vhdl , are introduced . also , expatiated the inner modules structure of fpga for forepart circuit , the keystone and difficulties of the design . the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system , and it is very important . the timing simulating results of several pivotal modules are depicted . high - speed signal paths are terminated to match the characteristic impedance . the design undergoes integrity analysis and software simulation
在本模块的设计中,有着大量的逻辑设计,对硬件语言程序的编写要求比较高,因此,文中介绍了硬件程序设计的基本流程,以及几种基于vhdl硬件语言设计在高速逻辑设计中非常重要的方法。同时阐述了本模块设计的前端fpga的内部模块结构,设计的重点、难点,并给出了重要模块的时序仿真结果。高速pcb的设计也是目前实现高速数据采集系统的难点和重点,文中详细的阐明了高速pcb设计中的注意点,以及作者在设计本模块时的经验和心得。
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